HY5DU283222BF Datasheet | SK Hynix

description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 1.0 / Feb. 2005 1HY5DU283222BF(P) Revision History No. History 0.1 1) Defined Target Spec. 0.2 1) Added 200MHz speed bin 0.3 1) Changed Cas Latency to 4 clock from 5 clock at 300Mhz/275Mhz/ 250Mhz speed bin 0.4 1) Changed IDD & 500Mhz speed bin insert, 2) Changed t RCDWR, t WR at 450Mhz speed bin 1.0 1) Changed IDD Spec. 2) Changed CAS Latency to 4 clock from 5 clock at 350MHz speed bin Draft Date Jun. 2004 Jun. 2004 Sep. 2004 Remark Oct. 2004 Feb. 2005 Rev. 1.0 / Feb. 2005 1HY5DU283222BF(P) DESCRIPTION The Hynix HY5DU283222 is a 134,217,728-bit CMOS Double Data Rate(DDR) Synchronous DRAM, ideally suited for the point-to-point applications which requires high bandwidth. The Hynix 4Mx32 DDR SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the /CK), Data, Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are internally pipelined and 2-bit prefetched to achieve very high bandwidth. All input and output voltage levels are patible with SSTL_2. FEATURES - The Hynix HY5DU283222BF(P) guarantee until 200MHz speed at DLL_off condition - 2.5V VDD and VDDQ wide range max power supply supports - All inputs and outputs are patible with SSTL_2 interface - 12mm x 12mm, 144ball FBGA with 0.8mm pin pitch - Fully differential clock inputs (CK, /CK) operation - Double data rate interface - Source synchronous - data transaction aligned to bidirectional data strobe (DQS0 ~ DQS3) - Data outputs on DQS edges when read (edged DQ) Data inputs on DQS centers when write (centered DQ) - Data(DQ) and Write masks(DM) latched on the both rising and falling edges of the data strobe - All addresses and...